1. Field of the Invention
Generally, the present invention relates to the fabrication of integrated circuits, and, more particularly, to the formation of sidewall spacer elements used to, for instance, laterally pattern a dopant profile implanted adjacent to a circuit element having formed thereon the sidewall spacer elements.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of process steps involving photolithography, etch techniques, implantation sequences, anneal cycles and the like. In MOS technology, one important step is the formation of a gate electrode of a field effect transistor, wherein the size of the gate electrode significantly affects the overall performance of the MOS transistor element. The gate electrode is a line-like circuit element formed above a crystalline semiconductor region, typically a silicon region, wherein a thin gate insulation layer is disposed between the semiconductor region and the gate electrode so as to provide a dielectric barrier and generate a capacitive coupling to the underlying semiconductor region that forms a conductive channel upon application of an appropriate control voltage to the gate electrode. The channel forms in the semiconductor region in the vicinity of the gate insulation layer and establishes an electrical connection between highly doped source and drain regions. The distance between the drain and source regions, i.e., the lateral extension of the channel, which is correlated with the lateral extension of the gate electrode, also referred to as channel length, is an important design parameter and has now reached 0.1 μm and less in sophisticated integrated circuits.
In standard MOS technology, the gate electrode is formed prior to the formation of the drain and source regions by ion implantation. During the ion implantation process, the gate electrode acts as an implantation mask, thereby ensuring a correct alignment of the drain and source regions with respect to the gate electrode. Since a plurality of high temperature treatments will be performed after the formation of the gate electrode, the gate insulation layer formed prior to the patterning of the gate electrode is preferably manufactured on the basis of silicon dioxide or silicon nitride, and the gate electrode is made of polysilicon to obtain a gate electrode structure exhibiting a high thermal stability. After the patterning of the gate electrode, the drain and source regions are formed by ion implantation while using the gate electrode as an implantation mask. It turns out, however, that transistor elements of reduced feature sizes require sophisticated dopant profiles in the lateral direction and also in the vertical direction, wherein the term “vertical” describes the direction perpendicular to the surface of the substrate while the term “lateral” roughly corresponds to the flow direction of charge carriers in the channel. While the vertical dopant profiling may be achieved by correspondingly adjusting the implantation parameters, such as dose and energy for a given ion species, the lateral dopant profiling requires an enhanced masking technique, which is typically accomplished with the formation of one or more sidewall spacer elements.
With reference to FIGS. 1a–1c, a typical conventional process for forming sidewall spacer elements will now be described in more detail so as to discuss certain inefficiencies of the conventional technology when feature sizes of circuit elements are further scaled down. FIG. 1a is a schematic cross-sectional view of a transistor element 100 at an early manufacturing stage. The transistor element 100 comprises a substrate 101, which may be a silicon substrate or a silicon-on-insulator (SOI) substrate in sophisticated devices. Irrespective of the type of substrate used, the substrate 101 comprises a substantially crystalline semiconductor region 103 which is enclosed by an isolation structure 102, which is typically provided in modern integrated circuits in the form of a trench isolation. The transistor element 100 further includes a gate electrode 105 comprised of polysilicon and formed above the silicon region 103 and separated therefrom by a gate insulation layer 104. In principle, the reduction of the gate length, i.e., in FIG. 1a, the horizontal extension of the gate electrode 105, requires a corresponding reduction of a thickness of the gate insulation layer 104 to ensure appropriate capacitive coupling for proper control of a channel forming below the gate insulation layer 104 upon application of an appropriate control voltage. For a gate length of approximately 100 nm, the thickness of the gate insulation layer 104, when comprised of silicon dioxide, is in the range from about 2–4 nm. In view of proper channel controllability and in order to maintain the integrity of the gate insulation layer 104, highly sophisticated implantation profiles are required adjacent to the gate electrode 105. To this end, a sidewall spacer element 106, frequently referred to as an offset spacer, is formed on the sidewalls of the gate electrode 105 to act in combination with the gate electrode 105 as an implantation mask during a first implantation, indicated by 108. The corresponding dopant profile, indicated by 107, will also be referred to as an extension region.
A typical process flow for forming the transistor element 100 as shown in FIG. 1a may comprise the following processes. First, the trench isolations 102 are formed in the substrate 101 by sophisticated photolithography, anisotropic etch and deposition techniques, as are well established in the art. Thereafter, a plurality of implantation cycles may be performed to establish a required vertical dopant profile (not shown) within the semiconductor region 103. Thereafter, a material layer for the gate insulation layer 104 is formed on the substrate 101, for instance by sophisticated oxidation and/or deposition techniques. Next, a layer of polysilicon is deposited with a required thickness by, for instance, low pressure chemical vapor deposition (LPCVD) on the basis of process parameters as are well established in the art. Subsequently, the polysilicon layer and the material layer for the gate insulation layer 104 are patterned by sophisticated photolithography and anisotropic etch techniques, wherein, typically, a resist feature is formed first and is trimmed to specified dimensions to act as an etch mask during the subsequent anisotropic etch process, during which the gate electrode 105 is formed from the polysilicon layer, while the material layer for the gate insulation layer 104 serves as an etch stop layer. Thereafter, the residuals of the material layer forming the gate insulation layer 104 may be removed and the substrate 101 may be oxidized (not shown) to form a thin silicon dioxide layer on exposed surfaces of the silicon region 103 and the gate electrode 105. Next, a silicon dioxide layer may be conformally deposited and then anisotropically etched selectively to silicon to form the offset spacers 106. Thereby, the width of the offset spacer 106 and, thus, the lateral blocking effect thereof, is determined by the thickness of the deposited silicon dioxide layer. Finally, using the gate electrode 105 and the offset spacers 106 as an implantation mask, the implantation 108 is performed to define the extension regions 107, the dopant profile of which is determined in the vertical direction by the type of dopants used and the corresponding implantation energy, and in the lateral direction by the offset spacers 106.
FIG. 1b schematically shows the transistor element 100 in an advanced manufacturing stage. A spacer layer 110, for instance comprised of silicon nitride, is conformally formed above the substrate 101 and the gate electrode 105 with a thickness as required for further profiling of the lateral dopant concentration in the semiconductor region 103. Moreover, a thin etch stop layer 109, comprised of silicon dioxide, is disposed between the spacer layer 110 and the substrate 101. A typical process includes the deposition of the etch stop layer 109 by plasma enhanced chemical vapor deposition followed by plasma enhanced chemical vapor deposition of the spacer layer 110. Since the lateral dopant profiling depends on the accuracy of the deposition of the spacer layer 110, silicon nitride is the preferred candidate as this material may be deposited by well-established CVD techniques more precisely compared to, for instance, silicon dioxide. After the deposition of the layers 109 and 110, an anisotropic etch process is performed with an appropriately selected etch chemistry exhibiting a moderately high etch selectivity between the etch stop layer 109 and the spacer layer 110. Owing to the ever decreasing feature sizes, the thickness of the spacer layer 110 and also of the etch stop layer 109, have to correspondingly be adapted to the reduced feature sizes so that a thickness of the etch stop layer 109 is typically in the range of 1–5 nm.
FIG. 1c schematically shows the transistor element 100 after the anisotropic etch process, wherein the spacer layer 110 is substantially removed except for portions at the sidewall of the gate electrode 105, which are also denoted as sidewall spacers 110a. While for increased feature sizes and thus increased thicknesses of the layers 109 and 110, typically the thickness of the thin etch stop layer 109 is sufficient to reliably stop the etch front when substantially completely removing the excess material of the spacer layer 110 from horizontal surface portions, since the etch stop layer 109 only has to slow down the etch process at the exposed portions until all of the spacer layer 110 material is removed across the entire substrate 101, the situation is different for extremely scaled devices. In this case, the deposited etch stop layer 109, e.g., silicon dioxide, may, owing to the reduced thickness, provide local “channels” through which the etch chemistry may attack the surface portion of the region 103 and the gate electrode 105, thereby generating a “pitting” effect.
As previously explained, the gate electrode 105, although highly doped, exhibits a relatively low conductivity compared to, for instance, metals such as aluminum, tungsten and the like as are typically used in semiconductor fabrication. Consequently, in a typical MOS technology, the conductivity of the gate electrode 105 is increased by forming a metal silicide region on the gate electrode 105 to reduce the resistivity thereof. During the silicidation process, the sidewall spacer 110a additionally serves the purpose of allowing a self-aligned formation of metal silicide in the drain and source regions to be formed and in the gate electrode 105, since a silicide formation on the sidewall spacer 110a is substantially prevented. As the amount of metal silicide formed in the gate electrode 105 in the subsequent process may, depending on the process specifics, be determined based on the size of exposed silicon area of the gate electrode 105, in some process flows, the anisotropic etch process is continued to further reduce the vertical extension of the spacer element 110a while substantially maintaining the lateral width thereof. During the continuation of the anisotropic etch process, exposed portions of the etch stop layer 109 are increasingly consumed due to the limited etch selectivity, thereby still further increasing the pitting effect and severely jeopardizing the integrity of the underlying material surfaces.
FIG. 1d schematically shows the transistor element 100 after completion of the above-described anisotropic etch process. The sidewall spacers 110a exhibit a significantly reduced vertical extension to expose upper sidewall portions of the gate electrode 105, which are still covered by residuals of the etch stop layer 109 and the offset spacers 106, which will be removed in a subsequent isotropic wet chemical etch process on the basis of, for instance, hydrogen fluoride. Moreover, exposed portions of the etch stop layer 109, indicated as 109a, show a significantly reduced thickness and may result in pitting, indicated as 111, of the underlying material. The locally inhomogeneous damage, i.e., the pitting 111, is disadvantageous for the further processing of the transistor element 100, as, for instance, the mechanical and electrical characteristics of the surface portions involved are significantly degraded. In extremely scaled transistor elements, the available surface area for forming contacts is also extremely reduced, and undue transistor performance deterioration may be observed that is caused by surface portions damaged by pittings 111 during the spacer etch sequence. Moreover, the problem is exacerbated in sophisticated transistor elements where more than two spacer elements, such as the offset spacer 106 and the spacer 110a, have to be formed in order to assure the required lateral profiling in the semiconductor region 103. Hence, in a subsequent patterning process for further sidewall spacers, which may also be anisotropically etched until upper sidewall portions of the gate electrode 105 are exposed, a further degradation of exposed surface portions by, for example, pitting is obtained. Reducing the effect of pitting during the anisotropic etching by, for instance, increasing the thickness of the etch stop layer 109, is less than desirable, since the subsequent isotropic removal of residues of the layer 109 and the offset spacers 106 would then result in a non-tolerable under-etch of the sidewall spacer 110a. Moreover, increasing the thickness of the layer 109 at the expense of reducing the thickness of the spacer layer 110 may result in reduced controllability of the lateral dopant profiling.
In view of the above-identified problems, there exists a need for an improved technique for forming sidewall spacer elements, thereby reducing the damage caused in exposed surface portions during the anisotropic patterning of a spacer layer.